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Electrical Engineering Software
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SpiceCut by
Legend Design Technology Inc
SpiceCut is a leading edge solution for automation in generating accurate critical
path circuits for spice simulations.
http://www.LegendDesign.com
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ProGenesis by
PROLIFIC, Inc
Standard-cell library development is made easy with ProGenesis, a comprehensive,
generator-based tool suite that takes your SPICE netlist input and produces GDS
layout for as many process technologies as you wish. ProGenesis retains all edits
to your system, allowing you to incorporate design-rule changes quickly and easily.
http://www.prolificinc.com/products.shtml
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Vehicle Control Station by
CDL Systems
The Vehicle Control Station (VCS) is a truly portable, fully integrated command,
control and information system designed for the control of unmanned vehicles (UVs)
and remote surveillance in both manned and unmanned applications.
http://www.cdlsystems.com
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Debussy(r) Total Debug System by
NOVAS Software Inc.
Debussy(r) is a complete, open debug system for Verilog and VHDL designs at the
gate, RTL, and behavioral levels. It improves debug productivity by making complex
designs easier to understand and by automating time-consuming debug tasks.
http://www.novas.com
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ApsimFDTD-SPICE by
Applied Simulation Technology
As operating frequencies reach 1GHz and beyond noise introduced from the interconnect
and power distribution system must accurately be accounted for in both PCB and IC
design. Such noise can destroy timing budgets and cause functional failures. Simulation
of these Signal Integrity issues has become a necessity.
http://www.apsimtech.com
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ApsimSI by
Applied Simulation Technology
Updated: 03/14/2001 ApsimSI can verify reflection and crosstalk noise along traces
in layout designs using the most accurate lossy coupled transmission line simulator
ApsimSPICE, fast transmission line parameter extractor ApsimRLGC and layout modeler
ApsimLIF. ApsimSI is integrated with PCB and MCM CAD systems http://www.apsimtech.com
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NeoCell by
Neo Linear Inc
NeoCell is the first automated solution for mixed-signal analog cell physical design.
NeoCell integrates an automated analog device-level place and route engine with
an interactive device-level layout, cell architecture, and physical constraint editor
to provide a highly productive environment for analog cell-level physical design.
http://www.neolinear.com/
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cadett ELSA by cadett
ab
Cadett ELSA is a complete system for electrical schematics for all categories of
users. cadett ELSA is easy to use. You can start by using cadett ELSA as a simple
and rational documentation tool. In the same time cadett ELSA will cover the need
of flexibility and automation of the most advanced users there is. http://www.cadett.se
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State Navigator by
TransEDA
State Navigator, the industry's first dedicated finite state machine (FSM) design,
debug and verification environment for Verilog and VHDL designs, provides simultaneous
debug of multiple, communicating state machines, behavioral FSM verification, static
FSM verification and FSM coverage. http://www.transeda.com
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Verification Navigator by
TransEDA
Verification Navigator, an integrated design verification environment that provides
code coverage, test suite optimization, state machine coverage, and circuit activity
analysis for Verilog, VHDL, and dual-language designs. http://www.transeda.com
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